Highly manufacturable 90 nm DRAM technology

被引：0

作者：

Park, YK ^{[1
]}

Cho, CH ^{[1
]}

Lee, KH ^{[1
]}

Roh, BH ^{[1
]}

Ahn, YS ^{[1
]}

Lee, SH ^{[1
]}

Oh, JH ^{[1
]}

Lee, JG ^{[1
]}

Kwak, DH ^{[1
]}

Shin, SH ^{[1
]}

Bae, JS ^{[1
]}

Kim, SB ^{[1
]}

Lee, JK ^{[1
]}

Lee, JY ^{[1
]}

Kim, MS ^{[1
]}

Lee, JW ^{[1
]}

Lee, DJ ^{[1
]}

Hong, SH ^{[1
]}

Bae, DI ^{[1
]}

Chun, YS ^{[1
]}

Park, SH ^{[1
]}

Yun, CJ ^{[1
]}

Chung, TY ^{[1
]}

Kim, K ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Technol Dev, Semicond R&D Div, Yongin 449900, Kyunggi Do, South Korea

来源：

INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 90 nm DRAM technology has been successfully developed using 512Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. Diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make back-end metallization process simple and easy. Dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of cell transistor can be maintained below 0.1 fA.

引用

页码：819 / 822

页数：4

共 50 条

[1] An outstanding and highly manufacturable 80nm DRAM technology
Kim, HS
Kim, DH
Park, JM
Hwang, YS
Huh, M
Hwang, HK
Kang, NJ
Lee, BH
Cho, MH
Kim, SE
Kim, JY
Park, BJ
Lee, JW
Kim, DI
Jeong, MY
Kim, HJ
Park, YJ
Kim, K
[J]. 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, : 411 - 414
[2] Highly manufacturable 4Gb DRAM using 0.11μm DRAM technology
Jeong, HS
Yang, WS
Hwang, YS
Cho, CH
Park, S
Ahn, SJ
Chun, YS
Shin, SH
Song, SH
Lee, JY
Jang, SM
Lee, CH
Jeong, JH
Cho, MH
Lee, JK
Kim, K
[J]. INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 353 - 356
[3] Highly reliable interconnect technology featuring 90nm DRAM integration
Chung, UI
Choi, S
Choi, GH
[J]. PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, : 247 - 249
[4] Highly manufacturable sub-100nm DRAM integrated with full functionality
Choi, S
Nam, BY
Ku, JH
Kim, DC
Lee, SH
Lee, JJ
Lee, JW
Ryu, JD
Heo, SJ
Cho, JK
Yoon, SP
Choi, CJ
Lee, YJ
Chung, JH
Kim, BH
Lee, MB
Choi, GH
Kim, YS
Fujihara, K
Chung, UI
Moon, JT
[J]. 2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 54 - 55
[5] A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology
Amon, J
Kieslich, A
Heineck, L
Faul, TSJ
Luetzen, J
Fan, C
Huang, CC
Fischer, B
Enders, G
Kudelka, S
Schroeder, U
Kuesters, KH
Lange, G
Alsmeier, J
[J]. IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 73 - 76
[6] Highly manufacturable 90 nm NOR flash multi-level cell technology with WSix gate
Song, Yun Heub
Park, Jeong Ho
Lee, Sang Eun
Lee, Jun Young
Shin, Joong Shik
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, 2007, 46 (4-7): : L120 - L122
[7] Full integration of highly manufacturable 512Mb PRAM based on 90nm technology
Oh, J. H.
Park, J. H.
Lim, Y. S.
Lim, H. S.
Oh, Y. T.
Kim, J. S.
Shin, J. M.
Park, J. H.
Song, Y. J.
Ryoo, K. C.
Lim, D. W.
Park, S. S.
Kim, J. I.
Kim, J. H.
Yu, J.
Yeung, F.
Jeong, C. W.
Kong, J. H.
Kang, D. H.
Koh, G. H.
Jeong, G. T.
Jeong, H. S.
Kim, Kinarn
[J]. 2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 515 - +
[8] NEC unveils 90-nm embedded DRAM technology
不详
[J]. AMERICAN CERAMIC SOCIETY BULLETIN, 2005, 84 (05): : 6 - 6
[9] A highly manufacturable 110nm DRAM technology with 8F2 vertical transistor cell for 1Gb and beyond
Akatsu, H
Weis, R
Cheng, K
Seitz, M
Kim, MS
Ramachandran, R
Dyer, T
Kim, B
Kim, DK
Malik, R
Strane, J
Goebel, T
Kwon, OJ
Sung, CY
Parkinson, P
Wilson, K
McStay, I
Chudzik, M
Dobuzinsky, D
Jacunski, M
Ransom, C
Settlemyer, K
Economikos, L
Simpson, A
Knorr, A
Naeem, M
Stojakovic, G
Robl, W
Gluschenkov, O
Liegl, B
Wu, CH
Wu, Q
Li, WK
Choi, CJ
Arnold, N
Joseph, T
Varn, K
Weybright, M
McStay, K
Kang, WT
Li, Y
Bukofsky, S
Jammy, R
Schutz, R
Gutmann, A
Bergner, W
Divakaruni, R
Back, D
Crabbe, E
Mueller, W
[J]. 2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2002, : 52 - 53
[10] A highly manufacturable capacitor-less IT-DRAM concept
Fazan, PC
Okhonin, S
Nagoga, M
Sallese, JM
[J]. DESIGN, PROCESS INTEGRATION, AND CHARACTERIZATION FOR MICROELECTRONICS, 2002, 4692 : 489 - 502

← 1 2 3 4 5 →