共 50 条
- [42] Two-dimensional parity-based concurrent error detection method for AES against differential fault attack and its VLSI implementation Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2009, 46 (04): : 593 - 601
- [43] A new and efficient approach to protect AES against differential power analysis World Congr. Internet Secur., WorldCIS, 1600, (59-66):
- [45] Towards an AES crypto-chip resistant to differential power analysis ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2004, : 307 - 310
- [46] Differential power analysis attacks against AES circuits implemented on a FPGA ICIW 2007: PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON INFORMATION WARFARE AND SECURITY, 2007, : 117 - 122
- [47] An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES 2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2022, : 85 - 86
- [49] Deep Learning-Based Power Analysis Attack for Extracting AES Keys on ATmega328P Microcontroller Arabian Journal for Science and Engineering, 2024, 49 : 4197 - 4208