Two-dimensional parity-based concurrent error detection method for AES against differential fault attack and its VLSI implementation

被引：0
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作者：
Zhao, Jia [1 ]
Han, Jun [1 ]
Zeng, Xiaoyang [1 ]
Han, Lin [1 ]
机构：
[1] State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
来源：
Jisuanji Yanjiu yu Fazhan/Computer Research and Development | 2009年 / 46卷 / 04期
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页码：593 / 601
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