共 50 条
- [1] VLSI implementation of an AES algorithm resistant to differential power analysis attack ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 838 - 841
- [3] Differential Power Analysis and Differential Fault Attack Resistant AES Algorithm and its VLSI Implementation 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2212 - 2215
- [4] Power-analysis attack on an ASIC AES implementation ITCC 2004: INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: CODING AND COMPUTING, VOL 2, PROCEEDINGS, 2004, : 546 - 552
- [5] Differential fault analysis attack-tolerant hardware implementation of AES The Journal of Supercomputing, 2024, 80 : 4648 - 4681
- [6] Differential fault analysis attack-tolerant hardware implementation of AES JOURNAL OF SUPERCOMPUTING, 2024, 80 (04): : 4648 - 4681
- [8] Cache based AES attack implementation and its theoretical analysis Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2011, 48 (06): : 955 - 963
- [9] A Novel Correlation Power Analysis Attack on PIC Based AES-128 without Access to Crypto Device 2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 1320 - 1323
- [10] Neural Network Based Attack on a Masked Implementation of AES 2015 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), 2015, : 106 - 111