Modeling of on-chip bus switching current and its impact on noise in power supply grid

被引：4
|
作者：
Tuuna, Sampo [1 ]
Zheng, Li-Rong [2 ]
Isoaho, Jouni [1 ]
Tenhunen, Hannu [1 ]
机构：
[1] Univ Turku, Dept Informat Technol, Turku, Finland
[2] Royal Inst Technol, SE-16440 Stockholm, Sweden
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2008年 / 16卷 / 06期
关键词：
bus; power supply noise; transmission line;
D O I：
10.1109/TVLSI.2008.2000258
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance-inductance-capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.
引用
收藏
页码：766 / 770
页数：5
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