Full current-mode techniques for high-speed CMOS SRAMs

被引：0

作者：

Wang, SM ^{[1
]}

Wu, CK ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Hsinchu, Taiwan

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes an experimental 32Kx8 CMOS SRAM with a 9ns access time at a supply voltage of 3V using a 0.35um 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28mA at 100MHz under typical conditions.

引用

页码：580 / 582

页数：3

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