Current-mode analogue interface for high-speed low-current differential signalling

In this work, we propose high-speed low-current differential signalling (LCDS) over an electrical chip-to-chip interconnect by using a common-gate transimpedance amplifier followed by a common-source TIA stage. LCDS uses a current-mode receiver compared to a conventional voltage-mode receiver used in most of the signalling technologies such as low-voltage differential signalling, voltage-mode signalling and current-mode logic. The minimum detectable signal level possible with a current-mode receiver for the targeted bit-error rate (BER) makes LCDS an attractive choice. Also the input impedance of the LCDS receiver can be made equal to 100 differential for matching the characteristic impedance of electrical chip-to-chip interconnect. The complete design, analysis and noise characterisation of the TIA front-end is presented. The CGCSTIA is implemented in 1.8V, 0.18m digital CMOS technology. The input-referred noise current and 3-dB bandwidth of the receiver are 1.57A and 5.75GHz, respectively. For the targeted BER of 10-12, a data transfer rate of 6Gb/s is achieved, while transmitting the data over a FR4 PCB trace of length 20cm. The power dissipated in the current-mode receiver is 3.6mW.