Predictive placement scheme in set-associative cache for energy efficient embedded systems

被引:0
|
作者
Raveendran, Biju K. [1 ]
Sudarshan, T. S. B. [1 ]
Patil, Avinash [1 ]
Randive, Komal [1 ]
Gurunarayanan, S. [1 ]
机构
[1] BITS, Pilani 333031, Rajasthan, India
关键词
low power cache memory design; predictive placement; set associative cache; process aware cache;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a predictive placement scheme for set-associative cache with better way-prediction hit, energy efficiency and performance. In this work, we consider the data cache subsystem, as it is one of the most power consuming micro-architectural parts of an embedded system. We propose an energy efficient way-prediction scheme with predictive placement to improve prediction hit using minimal prediction bits. We show that, this scheme has an average energy saving 67.75% as compared to conventional caching scheme. Experimental results are obtained using Simplescalar 2.0 cache simulator for SPEC95 benchmarks.
引用
收藏
页码:152 / 157
页数:6
相关论文
共 50 条
  • [31] Variable-way set associative cache design for embedded system applications
    Aly, RE
    Nallamilli, BR
    Bayoumi, MA
    [J]. Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 1435 - 1438
  • [32] Energy-Efficient Cache Partitioning Using Machine Learning for Embedded Systems
    Nour, Samar
    Habashy, Shahira M.
    Salem, Sameh A.
    [J]. JORDAN JOURNAL OF ELECTRICAL ENGINEERING, 2023, 9 (03): : 285 - 300
  • [33] Enabling Energy Efficient Reliability in Embedded Systems Through Smart Cache Cleaning
    Jeyapaul, Reiley
    Shrivastava, Aviral
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2013, 18 (04)
  • [34] Way Guard: A Segmented Counting Bloom Filter Approach to Reducing Energy for Set-Associative Caches
    Ghosh, Mrinmoy
    Oezer, Emre
    Ford, Simon
    Biles, Stuart
    Lee, Hsien-Hsin S.
    [J]. ISLPED 09, 2009, : 165 - 170
  • [35] Low energy, highly-associative cache design for embedded processors
    Veidenbaum, A
    Nicolaescu, D
    [J]. IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS, 2004, : 332 - 335
  • [36] Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches
    Zhang, Wei
    Guan, Nan
    Ju, Lei
    Tang, Yue
    Liu, Weichen
    Jia, Zhiping
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (10) : 2333 - 2346
  • [37] Selective placement data cache for low energy embedded system
    Raveendran, Biju K.
    Sudarshan, T. S. B.
    Gurunarayanan, S.
    [J]. 2006 INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATIONS, VOLS 1 AND 2, 2007, : 460 - +
  • [38] Energy Prediction for Cache Tuning in Embedded Systems
    Vazquez, Ruben
    Gordon-Ross, Ann
    Stitt, Greg
    [J]. 2019 IEEE 37TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2019), 2019, : 630 - 637
  • [39] Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches
    Bardizbanyan, Alen
    Sjalander, Magnus
    Whalley, David
    Larsson-Edefors, Per
    [J]. 2013 IEEE 31ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2013, : 302 - 308
  • [40] Energy-Efficient Reconfigurable Cache Architectures for Accelerator-Enabled Embedded Systems
    Farmahini-Farahani, Amin
    Kim, Nam Sung
    Morrow, Katherine
    [J]. 2014 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS), 2014, : 211 - 220