Variable-way set associative cache design for embedded system applications

被引：0
|
作者：
Aly, RE [1 ]
Nallamilli, BR [1 ]
Bayoumi, MA [1 ]
机构：
[1] Univ Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA
来源：
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3 | 2003年
关键词：
cache design; set-associative cache; computer architecture; memory architecture;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Variable-way set associative cache is proposed as a new technique to maximize the cache performance especially for embedded applications or to reduce the power consumption with the same performance. Static profiling is used to determine the sets' behavior of the set-associative cache Variable-way set-associative can be used in High-performance or low-power operation modes. Each set in the proposed design basically has different associativity to maximize the total performance for the cache size or reduce the power consumption. The proposed architecture is simulated on simplescalar simulator and tested on several Spec2000 Benchmarks. The results show on average 2% reduction in the miss rate at the high-performance mode and up to 43% reduction of the power consumption at low-power mode.
引用
收藏
页码：1435 / 1438
页数：4
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