Predictive placement scheme in set-associative cache for energy efficient embedded systems

被引:0
|
作者
Raveendran, Biju K. [1 ]
Sudarshan, T. S. B. [1 ]
Patil, Avinash [1 ]
Randive, Komal [1 ]
Gurunarayanan, S. [1 ]
机构
[1] BITS, Pilani 333031, Rajasthan, India
关键词
low power cache memory design; predictive placement; set associative cache; process aware cache;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a predictive placement scheme for set-associative cache with better way-prediction hit, energy efficiency and performance. In this work, we consider the data cache subsystem, as it is one of the most power consuming micro-architectural parts of an embedded system. We propose an energy efficient way-prediction scheme with predictive placement to improve prediction hit using minimal prediction bits. We show that, this scheme has an average energy saving 67.75% as compared to conventional caching scheme. Experimental results are obtained using Simplescalar 2.0 cache simulator for SPEC95 benchmarks.
引用
收藏
页码:152 / 157
页数:6
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