Gate-Last I/O Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies

被引：3

作者：

Bhuiyan, M. ^{[1
]}

Kim, M. ^{[2
]}

Zhou, H. ^{[1
]}

Lo, H. ^{[2
]}

Siddiqui, S. ^{[1
]}

Stolfi, M. ^{[2
]}

Guarini, T. ^{[2
]}

Pujari, R. ^{[1
]}

Davey, E. ^{[2
]}

Stuckert, E. ^{[1
]}

Li, J. ^{[1
]}

Chou, A. ^{[1
]}

Zhao, K. ^{[1
]}

Wang, M. ^{[1
]}

Guo, D. ^{[1
]}

Colombeau, B. ^{[2
]}

Loubet, N. ^{[1
]}

Haran, B. ^{[2
]}

Bu, H. ^{[1
]}

机构：

[1] IBM Res, 257 Fuller Rd, Albany, NY 12203 USA

[2] Appl Mat Inc, 974 East Argues Ave, Sunnyvale, CA USA

来源：

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2021年

关键词：

D O I：

10.1109/IEDM19574.2021.9720507

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we demonstrate gate-all-around nanosheet based I/O transistors with a gate-last fabrication flow compatible with logic transistors using two different gate oxides: deposited oxide (DO) and selective oxide (SO). The novel selective oxidation process enables thick gate oxide foimation by expanding space between silicon sheets (T-sus). Advanced surface treatment techniques are used to enhance the drive current. Proper functioning of I/O devices at a starting T-sus of 12nm has been achieved for both NFETs and PFETs operation. The process flows presented in this paper result in I/O devices with excellent characteristics including low leakage, excellent PBTI, high breakdown voltage (V-bd) reaching >5.5 V and a good range of V-bd/maximum operation voltage (V-max) tunability.

引用

页数：4

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