A 5.2 GHz CMOS low noise amplifier with high-Q inductors embedded in wafer-level chip-scale package

被引：1
|
作者：
Fukuda, Satoshi [1 ]
Ito, Hiroyuki [2 ]
Itoi, Kazuhisa [3 ]
Sato, Masakazu [3 ]
Ito, Tatsuya [3 ]
Yamauchi, Ryozo [4 ]
Okada, Kenichi [1 ]
Masu, Kazuya [1 ]
机构：
[1] Tokyo Inst Technol, Integrated Res Inst, Midori Ku, 4259-R2-17 Nagatsuta, Yokohama, Kanagawa 2268503, Japan
[2] Tokyo Inst Technol, Precis & Intelligence Lab, Midori Ku, Yokohama 2268503, Japan
[3] Fujikura Ltd, Elect Device Lab, Chiba 2858550, Japan
[4] Fujikura Ltd, Tokyo 1358512, Japan
来源：
2007 IEEE INTERNATIONAL WORKSHOP ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY, PROCEEDINGS: ENABLING TECHNOLOGIES FOR EMERGING WIRELESS SYSTEMS | 2007年
关键词：
D O I：
10.1109/RFIT.2007.4443913
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a low noise amplifier (LNA) with high-Q inductors in a wafer-level chip-scale package (WL-CSP) process. Q-factor of inductors has big impacts on characteristics of LNAs, thus we investigate availability of WL-CSP high-Q inductors. A common-source LNA with inductive degeneration is used for discussion. The 5.2 GHz LNA with WL-CSP inductors provides a noise figure of 1.7 dB which is 1.5 dB smaller than that with on-chip inductors.
引用
收藏
页码：34 / +
页数：2
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