Robust Test Pattern Generation for Hold-time Faults in Nanometer Technologies

被引：0

作者：

Ho, Yu-Hao ^{[1
]}

Chen, Yo-Wei ^{[1
]}

Chang, Chih-Ming ^{[1
]}

Yang, Kai-Chieh ^{[1
]}

Li, James Chien-Mo ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Lab Dependable Syst LaDS, Taipei, Taiwan

来源：

2017 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | 2017年

关键词：

Hold-time Test; Robustness; Fault Model; ATPG; Fault Simulation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional path delay fault ATPG is not sufficient for hold-time faults. A hold-time fault ATPG is presented to generate robust test patterns. Experiments on large benchmark show that our test patterns are 42% shorter while 38% better in robust fault coverage than 1-detect stuck-at fault test sets. The results justify the need for hold-time fault ATPG.

引用

页数：4

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