A DC-50 GHz, Low Insertion Loss and High P1dB SPDT Switch IC in 40-nm SOI CMOS

被引：0
|
作者：
Chen, Cuilin [1 ]
Xu, Xiao [1 ]
Yoshimasu, Toshihiko [1 ]
机构：
[1] Waseda Univ, Grad Sch Informat Prod & Syst, Wakamatsu Ku, 2-7 Hibikino, Kitakyushu, Fukuoka, Japan
来源：
2017 IEEE ASIA PACIFIC MICROWAVE CONFERENCE (APMC) | 2017年
关键词：
broadband; SPDT switch IC; SOI; low insertion loss: high P1dB;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 (IB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.
引用
收藏
页码：5 / 8
页数：4
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