Analysis of various Full-Adder Circuits in Cadence

被引：0
|
作者：
Manjunath, K. M.
Haroon, Abdul Lateef P. S.
Pagi, Amarappa
Ulaganathan, J.
机构：
来源：
2015 INTERNATIONAL CONFERENCE ON EMERGING RESEARCH IN ELECTRONICS, COMPUTER SCIENCE AND TECHNOLOGY (ICERECT) | 2015年
关键词：
Cadence; Virtuoso; GPDK; Delay; Power Consumption; Area (Transistor Count);
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using cadence tool with the available GPDK -45nm kit. The Fulladder circuits with the most 28 transistor to the one with only 6 transistors are successfully designed, simulated and compared for various parameters like power consumption, speed of operation(delay) and area (transistor count), and finally concluded the best designs, that suite for the particular specifications.
引用
收藏
页码：90 / 97
页数：8
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