A 10Gb/s Inductorless Quarter-Rate Clock and Data Recovery Circuit in 0.13um CMOS

被引：4

作者：

Hsieh, Chang-Lin ^{[1
]}

Chu, Hong-Lin ^{[1
]}

Liu, Shen-Iuan ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10617, Taiwan

来源：

2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2009年

关键词：

PHASE-DETECTOR; CDR;

D O I：

10.1109/ASSCC.2009.5357217

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10Gb/s inductorless quarter-rate clock and data recovery (CDR) circuit is presented. In this CDR circuit, a triggering generator is proposed to realize the quarter-rate operation. Owing to the quarter-rate operation and the absence of inductors, this CDR circuit achieves low power consumption and small area simultaneously. This 10Gb/s quarter-rate CDR circuit has been fabricated in a 0.13um CMOS process. It recovers the data and clock within 5 bits. The measured peak-to-peak jitter of the recovered data and clock is 32.22ps and 30.7ps, respectively. The chip area including a PLL and a dummy GVCO is 0.2mm(2). This CDR circuit consumes 122.5mW excluding output buffers from a supply voltage of 1.5V.

引用

页码：165 / 168

页数：4

共 50 条

[1] A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector
Safari, Hamed
Baghtash, Hassan Faraji
Aghdam, Esmaeil Najafi
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2024, 119 (02) : 269 - 282
[2] A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector
Hamed Safari
Hassan Faraji Baghtash
Esmaeil Najafi Aghdam
[J]. Analog Integrated Circuits and Signal Processing, 2024, 119 : 269 - 282
[3] 20 Gb/s referenceless quarter-rate PLL-based clock data recovery circuit in 130 nm CMOS technology
Assaad, M.
Cumming, D. R. S.
[J]. MIXDES 2008: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, : 147 - 150
[4] A CMOS 10Gb/s clock and data recovery circuit with a novel adjustable KPD phase detector
Chen, XY
Green, MM
[J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 301 - 304
[5] A 10Gb/s CMOS half-rate clock and data recovery circuit with direct bang-bang tuning
Chen, Tun-Shih
[J]. 2005 IEEE International Workshop on Radio-Frequency Integration Technology, Proceedings: INTEGRATED CIRCUITS FOR WIDEBAND COMMUNICATION AND WIRELESS SENSOR NETWORKS, 2005, : 57 - 60
[6] A 10-gb/s CMOS clock and data recovery circuit
Savoj, J
Razavi, B
[J]. 2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2000, : 136 - 139
[7] A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector
Tan, Yung Sern
Yeo, Kiat Seng
Boon, Chirn Chye
Do, Manh Anh
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (06) : 1156 - 1167
[8] A Scalable 7.0-Gb/s Multi-Lane NRZ Transceiver with a 1/10th-Rate Forwarded Clock in 0.13um CMOS
Fiedler, Alan
Krishnan, Shoba
[J]. 2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2016, : 2330 - 2333
[9] 10 Gb/s linear full-rate CMOS phase detector for clock data recovery circuit
Yu, XP
Do, MA
Wu, R
Yeo, KS
Ma, JG
Yan, GQ
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2005, 45 (02) : 191 - 196
[10] Design and FPGA Implementation of PLL-based Quarter-rate Clock and Data Recovery Circuit
Alser, Mohammed H.
Assaad, Maher
Hussin, Fawnizu Azmadi
Yohannes, Israel
[J]. 2012 4TH INTERNATIONAL CONFERENCE ON INTELLIGENT AND ADVANCED SYSTEMS (ICIAS), VOLS 1-2, 2012, : 825 - 830

← 1 2 3 4 5 →