A 10Gb/s Inductorless Quarter-Rate Clock and Data Recovery Circuit in 0.13um CMOS

被引：4
|
作者：
Hsieh, Chang-Lin [1 ]
Chu, Hong-Lin [1 ]
Liu, Shen-Iuan [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10617, Taiwan
来源：
2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2009年
关键词：
PHASE-DETECTOR; CDR;
D O I：
10.1109/ASSCC.2009.5357217
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 10Gb/s inductorless quarter-rate clock and data recovery (CDR) circuit is presented. In this CDR circuit, a triggering generator is proposed to realize the quarter-rate operation. Owing to the quarter-rate operation and the absence of inductors, this CDR circuit achieves low power consumption and small area simultaneously. This 10Gb/s quarter-rate CDR circuit has been fabricated in a 0.13um CMOS process. It recovers the data and clock within 5 bits. The measured peak-to-peak jitter of the recovered data and clock is 32.22ps and 30.7ps, respectively. The chip area including a PLL and a dummy GVCO is 0.2mm(2). This CDR circuit consumes 122.5mW excluding output buffers from a supply voltage of 1.5V.
引用
收藏
页码：165 / 168
页数：4
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