85% endurance error reduction and data-retention lifetime enhancement by changing the reset voltage in 40 nm TaOx-based ReRAM

This paper proposes a changing reset voltage technique for 40 nm TaOx-based resistive random access memories (ReRAM). In the proposed technique, reset voltage (V-RESET) changes at high endurance such as 10(4) set/reset cycles. The changing reset voltage technique decreases the measured total bit-error rate (BER) of both the low resistance state (LRS) and high resistance state (HRS) by 85%, compared with conventional fixed reset voltage. In addition, the current difference between LRS and HRS at probability = 50% (window) increases by 57% with the proposed technique, which increases the read margin between set and reset. Moreover, by decreasing the tail bits and expanding the read margin, the data-retention lifetime is increased. As a result, the changing reset voltage technique is recommended for high endurance and long data retention lifetime. Finally, this paper proposes a physical model of the proposed technique. (C) 2020 The Japan Society of Applied Physics