Design of a 50 Gbit/s InP/InGaAs HBT master-slave D-type flip-flop

被引：0

作者：

Kasbari, A ^{[1
]}

André, P ^{[1
]}

Blayac, S ^{[1
]}

Riet, M ^{[1
]}

Konczykowska, A ^{[1
]}

Ouslimani, H ^{[1
]}

Godin, J ^{[1
]}

机构：

[1] OPTO, Grp Interet Econ, F-91460 Marcoussis, France

来源：

8TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE ELECTRON DEVICES FOR MICROWAVE AND OPTOELECTRONIC APPLICATIONS | 2000年

关键词：

D O I：

10.1109/EDMO.2000.919041

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design of a 50 Gbit/s master-slave D-type flip-flop for ETDM transmission system is presented. The chip is fabricated in an InP/InGaAs DHBT self-aligned technology with typical Ft and Fmax of about 160 GHz and 210 GHz respectively. We show how our design benefits at best from the available technology. The switching of the transistors is optimised as well as the sizing of basic blocks like emitter-followers or current switches. At this operating frequency, the layout step imposes to take into account propagation phenomena and interconnection parasitic elements, which necessarily degrade the performances. Appropriate methods are systematically applied to evaluate and reduce these effects.

引用

页码：105 / 110

页数：6

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