Design of a 50 Gbit/s InP/InGaAs HBT master-slave D-type flip-flop

被引:0
|
作者
Kasbari, A [1 ]
André, P [1 ]
Blayac, S [1 ]
Riet, M [1 ]
Konczykowska, A [1 ]
Ouslimani, H [1 ]
Godin, J [1 ]
机构
[1] OPTO, Grp Interet Econ, F-91460 Marcoussis, France
关键词
D O I
10.1109/EDMO.2000.919041
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The design of a 50 Gbit/s master-slave D-type flip-flop for ETDM transmission system is presented. The chip is fabricated in an InP/InGaAs DHBT self-aligned technology with typical Ft and Fmax of about 160 GHz and 210 GHz respectively. We show how our design benefits at best from the available technology. The switching of the transistors is optimised as well as the sizing of basic blocks like emitter-followers or current switches. At this operating frequency, the layout step imposes to take into account propagation phenomena and interconnection parasitic elements, which necessarily degrade the performances. Appropriate methods are systematically applied to evaluate and reduce these effects.
引用
收藏
页码:105 / 110
页数:6
相关论文
共 50 条
  • [1] 40 Gbit/s master-slave D-type flip-flop in InP DHBT technology
    Kasbari, A
    André, P
    Godin, J
    Konczykowska, A
    [J]. ELECTRONICS LETTERS, 2002, 38 (07) : 330 - 331
  • [2] Design of high speed master-slave D-type flip-flop in InP DHBT technology
    Kasbari, AE
    André, P
    Konczykowska, A
    Riet, M
    Blayac, S
    Ouslimani, H
    Godin, J
    [J]. 2002 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3, 2002, : 1057 - 1060
  • [3] Design of high-speed master-slave D-type flip-flop in InP DHBT technology
    Kasbari, AE
    André, P
    Konczykowska, A
    Riet, M
    Blayac, S
    Ouslimani, H
    Godin, J
    [J]. IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2002, 50 (12) : 3064 - 3069
  • [4] A Noise-tolerant Master-slave Flip-flop
    Miura, Yukiya
    Ohkawa, Yoshihiro
    [J]. PROCEEDINGS OF THE 2014 IEEE 20TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2014, : 55 - 61
  • [5] A static CMOS master-slave flip-flop experiment
    Vesterbacka, M
    [J]. ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 870 - 873
  • [6] SUB-MICRON SILICON BIPOLAR MASTER-SLAVE D-TYPE FLIP-FLOP FOR USE AS 8-1 GBIT/S DECISION CIRCUIT AND 11-2 GBIT/S DEMULTIPLEXER
    RUNGE, K
    GIMLETT, JL
    CLAWIN, D
    WAY, W
    CHEUNG, NK
    KIPNIS, I
    SNAPP, C
    [J]. ELECTRONICS LETTERS, 1989, 25 (20) : 1346 - 1347
  • [7] A CMOS Phase/Frequency Detector with a high-speed low-power D-type master-slave flip-flop
    Chen, YZ
    Tu, CH
    Wu, J
    [J]. 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, CONFERENCE PROCEEDINGS, 2002, : 389 - 392
  • [8] A 80-Gbit/s D-type flip-flop circuit using InPHEMT technology
    Suzuki, T
    Takahashi, T
    Hirose, T
    Takikawa, M
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (10) : 1706 - 1711
  • [9] A 80-Gbit/s D-type flip-flop circuit using InPHEMT technology
    Suzuki, T
    Takahashi, T
    Hirose, T
    Takigawa, M
    [J]. GAAS IC SYMPOSIUM - 25TH ANNUAL TECHNICAL DIGEST 2003, 2003, : 165 - 168
  • [10] 40-Gbit/s D-type flip-flop and multiplexer circuits using InPHEMT
    Suzuki, T
    Kano, H
    Nakasha, Y
    Takahashi, T
    Imanishi, K
    Ohnishi, H
    Watanabe, Y
    [J]. 2001 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2001, : 291 - 294