共 50 条
- [1] FPGA Implementation of Pipelined Architecture For SPIHT Algorithm 2013 IEEE INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN COMPUTING, COMMUNICATION AND NANOTECHNOLOGY (ICE-CCN'13), 2013, : 456 - 461
- [2] ARCHITECTURE OF A PIPELINED DATAPATH COARSE-GRAIN RECONFIGURABLE COPROCESSOR ARRAY ICSPC: 2007 IEEE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1-3, PROCEEDINGS, 2007, : 832 - 835
- [3] Design of pipelined architecture for hierarchical block-matching algorithm Kim, Hyung Chul, 1600, Inst of Electronics, Inf & Commun Engineers of Japan, Tokyo, Japan (E78-D):
- [8] An Efficient SPIHT Algorithm and System Architecture for Image Compression 2017 25TH SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE (SIU), 2017,
- [9] Architecture design of reconfigurable pipelined datapaths 20TH ANNIVERSARY CONFERENCE ON ADVANCED RESEARCH IN VLSI, PROCEEDINGS, 1999, : 23 - 40
- [10] A parallelized and pipelined datapath to implement ISODATA algorithm for rosette scan images on a reconfigurable hardware GRC: 2007 IEEE INTERNATIONAL CONFERENCE ON GRANULAR COMPUTING, PROCEEDINGS, 2007, : 433 - 436