Gated Diode Investigation of Bias Temperature Instability in High-κ FinFETs

被引：13
|
作者：
Young, Chadwin D. [1 ]
Neugroschel, Arnost [2 ]
Matthews, Kenneth [3 ]
Smith, Casey [1 ]
Heh, Dawei [1 ]
Park, Hokyung [1 ]
Hussein, Muhammad M. [1 ]
Taylor, William [1 ]
Bersuker, Gennadi [1 ]
机构：
[1] SEMATECH, Albany, NY 12203 USA
[2] Univ Florida, Gainesville, FL 32611 USA
[3] SVTC Technol, Austin, TX 78741 USA
来源：
IEEE ELECTRON DEVICE LETTERS | 2010年 / 31卷 / 07期
关键词：
Bias temperature instability (BTI); charge pumping; DCIV; FinFET; hafnium; high-kappa;
D O I：
10.1109/LED.2010.2049635
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n(+)/p(-)/p(+) structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be N-IT congruent to 1011 cm(-2) for SiO2/2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of Delta N-IT(t) under negative bias stress conditions (NBTI) suggests N-IT is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.
引用
收藏
页码：653 / 655
页数：3
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