Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS

被引:0
|
作者
Kennel, HW [1 ]
Cea, SM [1 ]
Lilak, AD [1 ]
Keys, PH [1 ]
Giles, MD [1 ]
Hwang, J [1 ]
Sandford, JS [1 ]
Corcoran, S [1 ]
机构
[1] Intel Corp, TCAD Div, Hillsboro, OR 97124 USA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents an integrated modeling approach to address diffusion and activation challenges in sub-90 nm CMOS technology. Co-implants of F and Ge are shown to reduce diffusion rates and a new model for the interactive effects is presented. Complex codiffusion behavior of As and P is presented and modeling concepts elucidated. Tradeoffs such as sheet resistance for a given junction depth, and how these depend on impurities, as well as soak vs. spike rapid thermal anneals (RTA), can be understood with simulation models.
引用
收藏
页码:875 / 878
页数:4
相关论文
共 50 条
  • [41] Continuity in the development of ultra shallow junctions for 130-45 nm CMOS: The tool and annealing methods
    Kuznetsov, VI
    van Zutphen, AJMM
    Kerp, HR
    Vermont, PG
    Pages, X
    van Hapert, JJ
    van der Jeugd, K
    Granneman, EHA
    11TH IEEE INTERNATIONAL CONFERENCE ON ADVANCED THERMAL PROCESSING OF SEMICONDUCTORS, 2003, : 63 - 74
  • [42] Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node
    Pawlak, BJ
    Lindsay, R
    Surdeanu, R
    Stolk, P
    Maex, K
    Pages, X
    IIT2002: ION IMPLANTATION TECHNOLOGY, PROCEEDINGS, 2003, : 21 - 24
  • [43] Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions
    Chakravarthi, S
    Kohli, R
    Chidambaram, R
    Bu, H
    Jain, A
    Hornung, B
    Machala, CF
    2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 159 - 162
  • [44] Laser activation of Ultra Shallow Junctions (USJ) doped by Plasma Immersion Ion Implantation (PIII)
    Vervisch, Vanessa
    Larmande, Yannick
    Delaporte, Philippe
    Sarnet, Thierry
    Sentis, Marc
    Etienne, Hasnaa
    Torregrosa, Frank
    Cristiano, Fuccio
    Fazzini, Pier Francesco
    APPLIED SURFACE SCIENCE, 2009, 255 (10) : 5647 - 5650
  • [45] Fabrication of N+/P ultra-shallow junctions by plasma doping for 65 nm CMOS technology
    Lallement, F
    Grouillet, A
    Juhel, M
    Reynard, JP
    Lenoble, D
    Fang, Z
    Walther, S
    Rault, Y
    Godet, L
    Scheuer, J
    SURFACE & COATINGS TECHNOLOGY, 2004, 186 (1-2): : 17 - 20
  • [46] Optimization of Flash Annealing Parameters to Achieve Ultra-Shallow Junctions for sub-45nm CMOS
    Kalra, Pankaj
    Majhi, Prashant
    Tseng, Hsing-Huang
    Jammy, Raj
    Liu, Tsu-Jae King
    DOPING ENGINEERING FOR FRONT-END PROCESSING, 2008, 1070 : 163 - +
  • [47] The effects of chemical bonding and band offset constraints at Si-dielectric interfaces on the integration of alternative high-K dielectrics into aggressively-scaled CMOS Si devices
    Lucovsky, G
    Phillips, JC
    MICROELECTRONIC ENGINEERING, 1999, 48 (1-4) : 291 - 294
  • [48] Schottky barrier characteristics of cobalt-nickel silicide/n-Si junctions for scaled-Si CMOS applications
    Panda, Debashis
    Dhar, Achintya
    Ray, Samit K.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (09) : 2403 - 2408
  • [49] Ultra-shallow p+-n junctions for 50-70 nm CMOS using selectively grown in-situ boron-doped silicon films
    Ban, I
    Öztürk, MC
    ADVANCES IN RAPID THERMAL PROCESSING, 1999, 99 (10): : 179 - 186
  • [50] Modeling of Thermal Processing at the Formation of Shallow Doped IC Active Regions
    Komarov, A. F.
    Velichko, O. I.
    Zayats, G. M.
    Komarov, F. F.
    Miskiewicz, S. A.
    Mironov, A. M.
    Makarevich, Yu. V.
    ACTA PHYSICA POLONICA A, 2013, 123 (05) : 804 - 808