Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS

被引:0
|
作者
Kennel, HW [1 ]
Cea, SM [1 ]
Lilak, AD [1 ]
Keys, PH [1 ]
Giles, MD [1 ]
Hwang, J [1 ]
Sandford, JS [1 ]
Corcoran, S [1 ]
机构
[1] Intel Corp, TCAD Div, Hillsboro, OR 97124 USA
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents an integrated modeling approach to address diffusion and activation challenges in sub-90 nm CMOS technology. Co-implants of F and Ge are shown to reduce diffusion rates and a new model for the interactive effects is presented. Complex codiffusion behavior of As and P is presented and modeling concepts elucidated. Tradeoffs such as sheet resistance for a given junction depth, and how these depend on impurities, as well as soak vs. spike rapid thermal anneals (RTA), can be understood with simulation models.
引用
收藏
页码:875 / 878
页数:4
相关论文
共 50 条
  • [31] HEAVILY DOPED ULTRA-SHALLOW JUNCTIONS FORMED BY AN ARF EXCIMER LASER
    YOSHIOKA, S
    WADA, J
    SAEKI, H
    MATSUMOTO, S
    LASER- AND PARTICLE-BEAM CHEMICAL PROCESSES ON SURFACES, 1989, 129 : 597 - 601
  • [32] Formation of counter doped shallow junctions by boron and antimony implantation and codiffusion in silicon
    Solmi, S
    Canteri, R
    DEFECTS AND DIFFUSION IN SILICON PROCESSING, 1997, 469 : 329 - 334
  • [33] SHALLOW JUNCTIONS, SILICIDE REQUIREMENTS AND PROCESS TECHNOLOGIES FOR SUB 0.5-MU-M CMOS
    DAVARI, B
    MICROELECTRONIC ENGINEERING, 1992, 19 (1-4) : 649 - 656
  • [34] VERY-SHALLOW LOW-RESISTIVITY P+-N JUNCTIONS FOR CMOS TECHNOLOGY
    LING, E
    MAGUIRE, PD
    GAMBLE, HS
    ARMSTRONG, BM
    IEEE ELECTRON DEVICE LETTERS, 1987, 8 (03) : 96 - 97
  • [35] Epitaxial n++-InGaAs ultra-shallow junctions for highly scaled n-MOS devices
    Tejedor, P.
    Drescher, M.
    Vazquez, L.
    Wilde, L.
    APPLIED SURFACE SCIENCE, 2019, 496
  • [36] Integration of alternative higk-K gate dielectrics into aggressively scaled CMOS Si devices: Chemical bonding constraints at Si-dielectric interfaces
    Lucovsky, G
    ADVANCES IN RAPID THERMAL PROCESSING, 1999, 99 (10): : 69 - 80
  • [37] CMOS application of Schottky source/drain SOI MOSFET with shallow doped extension
    Matsumoto, S
    Nishisaka, M
    Asano, T
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2004, 43 (4B): : 2170 - 2175
  • [38] Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits
    Ge, LX
    Fossum, JG
    Liu, B
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (09) : 2074 - 2080
  • [39] Advanced PMOS device architecture for highly-doped ultra-shallow junctions
    Surdeanu, R
    Pawlak, BJ
    Lindsay, R
    van Dal, M
    Doornbos, G
    Dachs, CJJ
    Ponomarev, YV
    Loo, JJP
    Cubaynes, FN
    Henson, K
    Verheijen, MA
    Kaiser, M
    Pages, X
    Stolk, PA
    Taylor, B
    Jurczak, M
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2004, 43 (4B): : 1778 - 1783
  • [40] Limitations for aggressively scaled CMOS Si devices due to bond coordination constraints and reduced band offset energies at Si-high-k dielectric interfaces
    Lucovsky, G
    Phillips, JC
    APPLIED SURFACE SCIENCE, 2000, 166 (1-4) : 497 - 503