Exploring the Advantages of Single-Ended-Input CMOS Self-Biased Amplifiers

This brief presents the analysis of self-biased topologies to implement single-ended-input CMOS amplifiers. We depart from basic amplifying stages to construct the self-biased circuits. We propose an amplifier based on the common-source and cascode configurations with active load, in which all three transistors are self-biased. This translates into important advantages for the amplifier: less power consumption since biasing circuits are no needed, and a robust design because all transistors are guaranteed to be in the saturation region even with process, temperature, or supply variations. The only drawback of this topology is the low power-supply rejection. A prototype was designed in a 130-nm CMOS technology to have a gain of 40 dB in the frequency band between 100 kHz and 5 MHz. The measurements of the circuit demonstrated that the amplifier fulfilled the specifications at the nominal voltage (1.2 V) while consuming 13. Furthermore, the circuit functions as amplifier for supply voltages as low as 400 mV and such high as 1.5 V, probing the flexibility of self-biased circuits. That flexibility can be explored in the future to design adaptive systems and to facilitate analog design automation.