On the speedup required for a multicast parallel packet switch

被引：12

作者：

Iyer, S ^{[1
]}

McKeown, N ^{[1
]}

机构：

[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA

来源：

IEEE COMMUNICATIONS LETTERS | 2001年 / 5卷 / 06期

基金：

美国国家科学基金会;

关键词：

Clos' network; inverse-multiplexing; load-balancing; multicasting; parallel packet switch;

D O I：

10.1109/4234.929609

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

A parallel packet switch (PPS) is a switch in which the memories run slower than the line rate. Arriving packets are load-balanced packet-by-packet over multiple lower speed center stage packet switches. It is known that, for unicast traffic, a PPS can precisely emulate a FCFS output-queued (OQ) switch with a speedup of two and an OQ switch with delay guarantees with a speedup of three. In this paper we ask: Is it possible for a PPS to emulate the behavior of an OQ multicast switch? The main result is that for multicast traffic an N-port PPS can precisely emulate a FIFO OQ switch with a speedup of S > 2 rootN+1, and a switch that provides delay guarantees with a speedup of S > 2 root 2N+2.

引用

页码：269 / 271

页数：3

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