A general design model for a practical parallel packet switch

被引:0
|
作者
Khodaparast, AA [1 ]
Khorsandi, S [1 ]
机构
[1] AmirKabir Polytech Univ, Dept Comp Eng & Informat Tech, Tehran, Iran
关键词
parallel packet switch; demultiplexer; backpressure; multistage switch; load balancing;
D O I
暂无
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
A Parallel Packet Switch (PPS) is a multistage switch aimed at building very high-speed switches using much slower devices. A PPS, in general, has three stages. Several packet-switches are placed in the central stage, which operate slower than the external line's rate. Incoming packets are spread over center stage switches by demultiplexers at the input stage. Packets destined to each output port need to be collected and reordered if necessary at the output stage. The initial PPS is proposed in [1], but it has several problems such as complexity and need of infinite buffers. To make the PPS practical, several design decisions need to be made. In this paper, we have developed a general design model for a practical PPS. Various aspects of a PPS design are explored and guidelines are provided. This model can help switch designers to make appropriate choices for each part within a general framework.
引用
收藏
页码:487 / 491
页数:5
相关论文
共 50 条
  • [1] Making multicast parallel packet switch practical
    Hu, XM
    Wang, BQ
    Jing, Y
    2005 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING PROCEEDINGS, VOLS 1 AND 2, 2005, : 1393 - 1397
  • [2] ANALYSIS AND DESIGN OF THE STABLE PARALLEL PACKET SWITCH
    Dong Yuguo Li Zupeng Guo Yunfei Wu Jiangxin (National Digital Switching System Eng. & Tech. R&D Center
    Journal of Electronics(China), 2005, (02) : 161 - 170
  • [3] ANALYSIS AND DESIGN OF THE STABLE PARALLEL PACKET SWITCH
    Dong Yuguo Li Zupeng Guo Yunfei Wu Jiangxin National Digital Switching System Eng Tech RD Center Info Univ Zhengzhou China Air Force Telecommunications Engineering Institute Xian China
    Journal of Electronics, 2005, (02) : 161 - 170
  • [4] Design and analysis of a fully-distributed parallel packet switch
    Khodaparast, AA
    Khorsandi, S
    2005 Asia-Pacific Conference on Communications (APCC), Vols 1& 2, 2005, : 188 - 192
  • [5] A MEMS based parallel packet switch
    Bauer, C
    Odame, K
    PROCEEDINGS OF THE IASTED INTERNATIONAL CONFERENCE ON WIRELESS AND OPTICAL COMMUNICATIONS, 2002, : 695 - 700
  • [6] Analysis of the parallel packet switch architecture
    Iyer, S
    McKeown, NW
    IEEE-ACM TRANSACTIONS ON NETWORKING, 2003, 11 (02) : 314 - 324
  • [7] Maintaining packet order for the parallel switch
    Dong, YG
    Wang, BQ
    Guo, YF
    Wu, JX
    GRID AND COOPERATIVE COMPUTING, PT 1, 2004, 3032 : 176 - 179
  • [8] Design of Parallel Packet Switch Simulation System Based on NS-2
    Yang, Fan
    Wang, Zhen-kai
    Chen, Jian-ya
    Liu, Yun-jie
    2009 5TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-8, 2009, : 4144 - 4147
  • [9] Making parallel packet switches practical
    Iyer, S
    McKeown, N
    IEEE INFOCOM 2001: THE CONFERENCE ON COMPUTER COMMUNICATIONS, VOLS 1-3, PROCEEDINGS: TWENTY YEARS INTO THE COMMUNICATIONS ODYSSEY, 2001, : 1680 - 1687
  • [10] Buffered Crossbar based Parallel Packet Switch
    Sun, Zhuo
    Karimi, Masoumeh
    Pan, Deng
    Yang, Zhenyu
    Pissinou, Niki
    2010 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE GLOBECOM 2010, 2010,