A 10-bit 100-MS/s 50mW CMOS A/D converter

被引：0

作者：

Tao, Z ^{[1
]}

Keramat, M ^{[1
]}

机构：

[1] Globespan Virata Corp, Santa Clara, CA 95051 USA

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high-speed and low-power pipelined analog-to-digital converter was designed and simulated with a 0.18mum CMOS technology. Techniques of scaling down sampling capacitors and using low accuracy dynamic comparators are employed to reduce the power dissipation. Simulation results-exhibit 10-bit operation at the sampling frequency of 100MHz with SNDR of 60dB, SFDR of 67dB and THD of 63dB at 2.34MHz input. For 46.1MHz input frequency, SNDR, SFDR and THD drop to 56dB, 64dB and 60dB respectively. The estimated power dissipation from a single 1.8V supply voltage is about 50mW.

引用

页码：121 / 124

页数：4

共 50 条

[41] A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique
Li, JP
Moon, UK
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (09) : 1468 - 1476
[42] A 10-bit 100MS/s pipelined ADC in 0.18μm CMOS technology
Lee, Hwei-Yu
Liu, Shen-Luan
20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2007, : 3 - +
[43] 10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter
Kim, Moo-Young
Kim, Jinwoo
Lee, Tagjong
Kim, Chulwoo
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (08) : 1438 - 1447
[44] A 400MS/s 10-bit Current-steering D/A Converter
Ren, Yannan
Li, Fule
Zhang, Chun
Wang, Zhihua
2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II: COMMUNICATIONS, NETWORKS AND SIGNAL PROCESSING, VOL I/ELECTRONIC DEVICES, CIRUITS AND SYSTEMS, VOL II, 2009, : 533 - 536
[45] A 10-bit, 20Ms/s, 22mW folding and interpolating CMOS ADC
Nabavi, AR
Dabbagh, K
ICM 2000: PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2000, : 43 - 46
[46] A 6-mW 10-bit 300 kSamples/s pipeline A/D-converter
Mantyniemi, A
Rahkonen, T
Ruha, A
PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 205 - 208
[47] A 10 BIT 50 MS/S CMOS D/A CONVERTER WITH 2.7-V POWER-SUPPLY
MIKI, T
NAKAMURA, Y
NISHIKAWA, Y
OKADA, K
HORIBA, Y
IEICE TRANSACTIONS ON ELECTRONICS, 1993, E76C (05) : 738 - 744
[48] A 10-bit 50-MS/s Asynchronous SAR ADC in 65nm CMOS
Zhao, Jiecheng
Huang, Zhixiang
Hou, Xueshi
2022 IEEE 14TH INTERNATIONAL CONFERENCE ON ADVANCED INFOCOMM TECHNOLOGY (ICAIT 2022), 2022, : 225 - 229
[49] A 4.7-mW 12-bit 100-MS/s Hybrid DAC
Wang, Wei
Zhang, Runxi
Shi, Chunqi
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 890 - 892
[50] A 10-bit, 500 MS/s, analog-to-digital converter
Sheng, NH
Yu, R
Chang, C
Cheng, K
Gutierrez, G
van der Wagt, P
Chang, MF
Rode, J
Nary, K
Nubling, R
1999 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-4, 1999, : 197 - 200

← 1 2 3 4 5 →