A 10-bit 100-MS/s 50mW CMOS A/D converter

被引：0

作者：

Tao, Z ^{[1
]}

Keramat, M ^{[1
]}

机构：

[1] Globespan Virata Corp, Santa Clara, CA 95051 USA

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A high-speed and low-power pipelined analog-to-digital converter was designed and simulated with a 0.18mum CMOS technology. Techniques of scaling down sampling capacitors and using low accuracy dynamic comparators are employed to reduce the power dissipation. Simulation results-exhibit 10-bit operation at the sampling frequency of 100MHz with SNDR of 60dB, SFDR of 67dB and THD of 63dB at 2.34MHz input. For 46.1MHz input frequency, SNDR, SFDR and THD drop to 56dB, 64dB and 60dB respectively. The estimated power dissipation from a single 1.8V supply voltage is about 50mW.

引用

页码：121 / 124

页数：4

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