A rail-to-rail low-power latch comparator with time domain bulk-tuned offset cancellation for low-voltage applications

被引:14
|
作者
Shahpari, Nima [1 ]
Habibi, Mehdi [1 ]
机构
[1] Univ Isfahan, Dept Elect Engn, Esfahan, Iran
关键词
bulk driven; comparator; dynamic level shifter; low power; offset cancellation; rail to rail; INPUT STAGE; SAR ADCS; DESIGN; AMPLIFIER;
D O I
10.1002/cta.2526
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Low-voltage high-precision comparators are the main building blocks of many low-power mixed-mode electronic devices. In this paper, a rail-to-rail high-precision comparator is introduced. The proposed comparator uses 2 parallel input P-type metal-oxide-semiconductor pairs with a dynamic level shifter to ensure rail-to-rail operation. Moreover, the proposed circuit incorporates a rail-to-rail offset cancellation circuit. The offset cancellation circuit works based on a time domain bulk-tuned negative feedback loop. The proposed comparator and offset cancellation circuits are designed to work correctly when the input common mode voltage varies from rail to rail. The rail-to-rail scheme allows the use of the proposed comparator in nanometer technologies, where the acceptable input range is limited. The proposed circuit was simulated in a standard 180nm complementary metal-oxide-semiconductor technology, and the results proved the rail-to-rail comparison ability in addition to the rail-to-rail offset cancellation function. The overall power consumption of the comparator was only increased by 11% compared with the conventional non-rail-to-rail approach. The maximum clock frequency of the proposed circuit is 833MHz, which is slightly more than its counterpart at similar operation conditions.
引用
收藏
页码:1968 / 1984
页数:17
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