Analysis of Parasitic Capacitance and Performance in Gate-All-Around and Tri-Gate Channel Vertical FET

被引：0
|
作者：
Seo, Youngsoo [1 ]
Kang, Myounggon [2 ]
Shin, Hyungcheol [1 ]
机构：
[1] Seoul Natl Univ, Dept Elect Engn & Comp Sci, Seoul 151742, South Korea
[2] Korea Natl Univ Transportat, Dept Elect Engn, Chungju City 380702, South Korea
来源：
2017 SILICON NANOELECTRONICS WORKSHOP (SNW) | 2017年
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel WET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
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页码：63 / 64
页数：2
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