共 50 条
- [41] Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect [J]. PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2023, GLSVLSI 2023, 2023, : 159 - 162
- [42] ASAP7 Predictive Design Kit Development and Cell Design Technology Co-optimization [J]. 2017 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2017, : 992 - 998
- [43] Process-Design Co-Optimization for FPGA [J]. 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2031 - 2034
- [44] Co-Optimization of Design and Fabrication Plans for Carpentry [J]. ACM TRANSACTIONS ON GRAPHICS, 2022, 41 (03):
- [45] Design and Technology Co-Optimization for exploring Power, Performance, Area and Manufacturability Trade-offs in Advanced FDSOI and FinFET Technologies [J]. 2018 IEEE 2ND ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2018), 2018, : 89 - 90
- [46] Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning [J]. 2021 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL INTERCONNECT PATHFINDING (SLIP 2021), 2021, : 8 - 15
- [47] Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue [J]. PROCEEDINGS OF THE 2016 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN (ISPD'16), 2016, : 89 - 89
- [50] New Memory Technology, Design and Architecture Co-optimization to Enable Future System Needs [J]. 2019 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2019,