A scheduling and partitioning scheme for low power circuit operating at multiple voltages

被引：0
|
作者：
Wang, L [1 ]
Selvaraj, H [1 ]
机构：
[1] Univ Nevada, Dept Elect & Comp Engn, Las Vegas, NV 89154 USA
来源：
EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS | 2003年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a scheme is presented to minimize power dissipation through scheduling and partitioning at the behavior level with resources operating at multiple voltages. The scheme uses partitioning to preserve locality in the assignment of operations to hardware units. Experimental results show that the proposed method can efficiently reduce power.
引用
收藏
页码：144 / 147
页数：4
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