共 50 条
- [31] Interactive built-in self-test compression for testing a system-on-a-chip IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2003, 150 (04): : 189 - 200
- [32] Instruction-level DFT for testing processor and IP cores in system-on-a-chip 38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 59 - 64
- [33] A software-based method for test vector compression in testing system-on-a-chip 2006 IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE PROCEEDINGS, VOLS 1-5, 2006, : 359 - +
- [34] A platform for system-on-a-chip design prototyping 2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 781 - 784
- [36] Special issue on system-on-a-chip - Preface FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2006, 42 (02): : 169 - 170
- [37] Integration architecture for System-on-a-Chip design IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 85 - 88
- [39] Design and Evaluation of A System-on-a-Chip Course 2016 11TH EUROPEAN WORKSHOP ON MICROELECTRONICS EDUCATION (EWME), 2016,