Self Driven Pass-Transistor based Low-Power Pulse Triggered Flip-Flop Design

In this paper, self driven pass-transistor based low-power pulse triggered flip-flop design is conferred. In this configuration, the creation of clock pulse is implemented with pass transistor based two input AND gate for reducing the discharging path and improve the speed, reduce the circuit complexity. In the proposed design input to output driving path inverter is deleted and the transistor is substituted with pass transistor logic. The pass transistor driven by generated clock pulse is utilized to drive the flip flop output. As compared to the conventional pulse triggered flip-flop, the proposed pulse triggered flip-flop design features are best speed, power and Power-Delay-Product (PDP) performance. It's maximum power saving against conventional pulse triggered flip-flop designs such as IPDCO, MHLFF, SCCER, CPE-PFF is up to 99.69%, 99.43%, 95.09%, 84.14% respectively at 100 MHZ input data rate. The proposed design is generated by using TSPICE CMOS 180nm process technology.