Theoretical and experimental investigation of a balanced phase-locked loop based clock recovery at a bit rate of 160 Gb/s

被引：0

作者：

Zibar, D ^{[1
]}

Oxenlove, LK ^{[1
]}

Clausen, AT ^{[1
]}

Mork, J ^{[1
]}

机构：

[1] Tech Univ Denmark, COM, DK-2800 Lyngby, Denmark

来源：

2003 IEEE LEOS ANNUAL MEETING CONFERENCE PROCEEDINGS, VOLS 1 AND 2 | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：388 / 389

页数：2

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