Analysis of thermal management in the system assembly of high density chip size packages

Driven by the demand for smaller, lighter and thinner products from consumer and portable electronics, the implementation of wafer level (chip size) package technologies pose a difficult challenge to thermal management issues on the system board. This paper presents an analysis of critical thermal management issues involved in the system assembly of high density wafer level packages. The growing heat removal requirements of semiconductor integrated circuits (ICs) as projected in the International Technology Roadmap for Semiconductors (ITRS) are examined. This is followed by a brief description of compliant wafer level package (CWLP) that is used as a chip size package in our analysis. In particular, the thermal performance of the package is presented. An analytic thermal model is qualitatively and quantitatively derived to study the heat transfer properties of the system comprising of IC, CWLP, and system board. The model is further developed to study the impact of heat sink and forced air convection on thermal management. The analytic model comprises of several parameters such as thermal properties of materials, thermal path distance, heat removal methodologies, heat sink designs in terms of material and fin geometry, and forced air velocity. These parameters aid in optimizing the system design to meet heat removal requirements as projected by the ITRS. The results of the model are utilized to calculate heat removal capabilities of the system with or without heat sink and identify critical bottlenecks in the heat flow path. Optimum package and heat sink design guidelines are determined to address the heat removal needs as projected in the ITRS. Novel heat sink designs and/or high aspect ratio (500-100) fin designs have to be employed for efficient thermal management for wafer level packages.