Family of fast mixed arithmetic logic transforms for multiple-valued input binary functions

被引：3
|
作者：
Rahardja, S [1 ]
Falkowski, BJ [1 ]
机构：
[1] NANYANG TECHNOL UNIV,SCH ELECTR & ELECT ENGN,SINGAPORE 639798,SINGAPORE
来源：
1996 26TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/ISMVL.1996.508331
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
引用
收藏
页码：24 / 29
页数：6
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