Real-Time Memory Controller for Embedded Multi-core System

被引：2

作者：

Mohamed, Ahmed S. S. ^{[1
]}

El-Moursy, Ali A. ^{[2
]}

Fahmy, Hossam A. H. ^{[1
]}

机构：

[1] Cairo Univ, Elect & Commun Engn Dept, Cairo, Egypt

[2] Univ Sharjah, Elect & Comp Engn Dept, Sharjah, U Arab Emirates

来源：

2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS) | 2015年

关键词：

Real-Time; Memory Controller; CMPs;

D O I：

10.1109/HPCC-CSS-ICESS.2015.133

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Nowadays modern chip multi-cores (CMPs) become more demanding because of their high performance especially in real-time embedded systems. On the other side, bounded latencies has become vital to guarantee high performance and fairness for applications running on CMPs cores. We propose a new memory controller that prioritizes and assigns defined quotas for cores within unified epoch (MCES). Our approach works on variety of generations of double data rate DRAM (DDR DRAM). MCES is able to achieve an overall performance reached 35% for 4 cores system.

引用

页码：839 / 842

页数：4

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