A Hard Real-Time Capable Multi-Core SMT Processor

被引：10

作者：

Paolieri, Marco ^{[1
]}

Mische, Joerg ^{[2
]}

Metzlaff, Stefan ^{[2
]}

Gerdes, Mike ^{[2
]}

Quinones, Eduardo ^{[3
]}

Uhrig, Sascha ^{[4
]}

Ungerer, Theo ^{[2
]}

Cazorla, Francisco J. ^{[5
]}

机构：

[1] Univ Politecn Cataluna, Barcelona Supercomp Ctr, E-08028 Barcelona, Spain

[2] Univ Augsburg, Augsburg, Germany

[3] Barcelona Supercomp Ctr, Barcelona, Spain

[4] Tech Univ Dortmund, Dortmund, Germany

[5] Spanish Natl Res Council, Barcelona Supercomp Ctr, Barcelona, Spain

来源：

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | 2013年 / 12卷 / 03期

关键词：

Design; Performance; Multi-core; SMT; multithreading; real-time; worst-case execution time;

D O I：

10.1145/2442116.2442129

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.

引用

页数：26

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