Model generation of test logic for macrocell based designs

被引：1
|
作者：
delaTorre, E [1 ]
Calvo, J [1 ]
Uceda, J [1 ]
机构：
[1] UNIV POLITECN MADRID,ETSI IND MADRID,MADRID 28006,SPAIN
来源：
EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/EURDAC.1996.558243
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
引用
收藏
页码：456 / 461
页数：6
相关论文
共 50 条
  • [31] Bandwidth-Aware Test Compression Logic for SoC Designs
    Janicki, Jakub
    Tyszer, Jerzy
    Mrugalski, Grzegorz
    Rajski, Janusz
    2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
  • [32] An automatic test system model based on linear temporal logic
    Hu, Y
    Chen, GJ
    ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 571 - 576
  • [33] Improving Model-Based Test Generation by Model Decomposition
    Arcaini, Paolo
    Gargantini, Angelo
    Riccobene, Elvinia
    2015 10TH JOINT MEETING OF THE EUROPEAN SOFTWARE ENGINEERING CONFERENCE AND THE ACM SIGSOFT SYMPOSIUM ON THE FOUNDATIONS OF SOFTWARE ENGINEERING (ESEC/FSE 2015) PROCEEDINGS, 2015, : 119 - 130
  • [34] SXM-Based Web Test Generation with Respect to Logic Coverage Criteria
    Qian Zhongsheng
    INTERNATIONAL JOURNAL OF SOFTWARE ENGINEERING AND KNOWLEDGE ENGINEERING, 2017, 27 (04) : 539 - 573
  • [35] Test input generation of bitwise operation based on four-valued logic
    Li F.
    Wang Y.
    Gong Y.
    Li, Feng (643581556@qq.com), 2018, Taylor and Francis Ltd. (40) : 1 - 8
  • [36] Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic
    Erb, Dominik
    Scheibler, Karsten
    Kochte, Michael A.
    Sauer, Matthias
    Wunderlich, Hans-Joachim
    Becker, Bernd
    2014 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2014,
  • [37] Level-oriented GA-based test generation of logic circuits
    Long, WN
    Yang, SY
    Min, YH
    Tong, SB
    1997 IEEE INTERNATIONAL CONFERENCE ON INTELLIGENT PROCESSING SYSTEMS, VOLS 1 & 2, 1997, : 563 - 567
  • [38] TEST PATTERN GENERATION FOR CMOS TERNARY LOGIC
    ROZON, C
    MOUFTAH, HT
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1988, 65 (02) : 155 - 163
  • [39] TEST-GENERATION THROUGH LOGIC PROGRAMMING
    SVANAES, D
    AAS, EJ
    INTEGRATION-THE VLSI JOURNAL, 1984, 2 (01) : 49 - 67
  • [40] Behavioral test generation for the selection of BIST logic
    Biasoli, G
    Ferrandi, F
    Fin, A
    Fummi, F
    Sciuto, D
    JOURNAL OF SYSTEMS ARCHITECTURE, 2002, 47 (10) : 821 - 829
12345