Model generation of test logic for macrocell based designs

被引：1
|
作者：
delaTorre, E [1 ]
Calvo, J [1 ]
Uceda, J [1 ]
机构：
[1] UNIV POLITECN MADRID,ETSI IND MADRID,MADRID 28006,SPAIN
来源：
EURO-DAC '96 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL '96 AND EXHIBITION, PROCEEDINGS | 1996年
关键词：
D O I：
10.1109/EURDAC.1996.558243
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
引用
收藏
页码：456 / 461
页数：6
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