Wafer warpage analysis of stacked wafers for 3D integration

被引：32

作者：

Kim, Youngrae ^{[2
]}

Kang, Sung-Keun ^{[2
]}

Kim, Sung-Dong ^{[2
,3
]}

Kim, Sarah Eunkyung ^{[1
]}

机构：

[1] Seoul Natl Univ Sci & Technol, Grad Sch NID Fus Technol, Seoul, South Korea

[2] Seoul Technopark, R&BD Div, Seoul, South Korea

[3] Seoul Natl Univ Sci & Technol, Sch Mech Design & Automat Engn, Seoul, South Korea

来源：

MICROELECTRONIC ENGINEERING | 2012年 / 89卷

关键词：

Wafer stacking; Warpage; Cu bonding; Coefficient of thermal expansion; 3D integration; STRESS;

D O I：

10.1016/j.mee.2011.01.079

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The demand for wafer stacking technology has been increasing significantly. Although many technical challenges of wafer stacking have improved greatly, there are still many processing issues to be resolved. One of them is wafer warpage since it causes process and product failures such as delamination, cracking, mechanical stresses, and even electrical failure. In this study the warpage of multi-stacked wafers has been evaluated. Three Si wafers have been stacked on a Si substrate using a thermo-compression Cu bonding. Each wafer stack was ground down to similar to 30 mu m and the thickness of the thinned Si wafer and wafer curvature were measured by FTIR (Fourier Transform Infrared Spectrometer) and FSM (Film-Stress Measurement), respectively. Wafer curvature becomes severe as the number of wafers in a stack increases, but the increment of wafer bow is reduced as the number of stack increases. The experimental results were also compared with the analytical model. (C) 2011 Elsevier B.V. All rights reserved.

引用

页码：46 / 49

页数：4

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