Hybrid Test Vector Compression in System-on-Chip Test - An Overview and Methodology

This paper presents a comprehensive study on a number of hybrid test vector compression methods for VLSI circuit testing. In the proposed approaches, a software program is loaded into the on-chip processor memory along with the compressed test data sets. To minimize on-chip storage besides testing time, the test data volume is first reduced by compaction in a hybrid manner before downloading into the processor. The methods utilize a set of adaptive coding techniques for realizing lossless compression. The compaction program need not be loaded into the embedded processor, as only the decompression of test data is required for the automatic test equipment. The developed schemes necessitate minimal hardware overhead, while the on-chip embedded processor can be reused for normal operation on completion of testing. As an extension of the earlier works, this paper also reports further results on studies of the problem and demonstrates the feasibility of the suggested methodologies with simulation results on ISCAS 85 combinational and ISCAS 89 full scan sequential benchmark circuits.