HDL Implementation of Turbo Decoder using Soft Output Viterbi Algorithm

This paper presents the design and implementation of an efficient VLSI architecture for 3GPP-LET. Turbo decoder mainly consists of soft-input soft-output (SISO) decoders to achieve high throughput and Convolutional interleaver. Turbo decoder comprises of Branch Metric Unit(BMU), State Metric unit(SMU), Log-Likelihood Ratio Computation Unit(LLR), Add Compare Select Unit. ACS (Add Compare & Select) unit is very important unit in terms of throughput. In this paper, a new ACS(Add Compare Select) unit consists of Carry-lookahed Adder, Digital Comparator & Multiplexer is used in Turbo Decoder which increases the throughput & reduces the area of the design. In data transmission, turbo coding helps achieve near Shannon limit performance. Turbo coding is an advanced error correction technique widely used in the communications industry. Turbo encoders and decoders are important blocks in today's communication systems to achieve the best possible data reception with the fewest possible errors. The proposed turbo decoder is based on the Soft Output Viterbi Algorithm (SOVA). The entire architecture of Turbo decoder is coded using Verilog HDL and it is synthesized using Xilinx EDA with Spartan 3E.