TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning

被引：5
|
作者：
Manna, Kanchan [1 ]
Teja, Vadapalli Shanmukha Sri [2 ]
Chattopadhyay, Santanu [2 ]
Sengupta, Indranil [3 ]
机构：
[1] Indian Inst Technol, Sch Informat Technol, Kharagpur 721302, W Bengal, India
[2] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India
[3] Indian Inst Technol, Dept Comp Sci, Kharagpur 721302, W Bengal, India
来源：
2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI | 2015年
关键词：
D O I：
10.1109/ISVLSI.2015.9
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Three-dimensional (3D) Network-on-Chip (NoC) based designs can utilize communication in vertical dimension to reduce distance between cores. Vertical connections are best implemented using Through-Silicon-Via (TSV). However, TSV geometry restricts the number of 3D routers in any layer of the die. This work proposes a strategy to select the TSV positions. This has been augmented by developing a core mapping procedure based on the Kernighan-Lin graph bi-partitioning algorithm, improved via an iterative improvement phase. The overall approach shows promising results compared to the existing mapping and TSV placement algorithms.
引用
收藏
页码：392 / 397
页数：6
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