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- [2] Optimal Number and Placement of Through Silicon Vias in 3D Network-on-Chip [J]. 2011 IEEE 14TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS), 2011, : 105 - 110
- [3] Reconfigurable Network-on-Chip for 3D Neural Network Accelerators [J]. 2018 TWELFTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2018,
- [4] Volumetric Degenerative Routing for 3D Network-on-Chip [J]. 2012 IEEE INTERNATIONAL CONFERENCE ON WIRELESS INFORMATION TECHNOLOGY AND SYSTEMS (ICWITS), 2012,
- [6] Exploring 3D Network-on-Chip Architectures and Challenges [J]. 2017 INTERNATIONAL CONFERENCE ON COMPUTER AND APPLICATIONS (ICCA), 2017, : 97 - 101
- [7] Through Silicon Via Placement and Mapping Strategy for 3D Mesh Based Network-on-Chip [J]. 2014 22ND INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2014,
- [8] A Method for Integrating Network-on-chip Topologies with 3D ICs [J]. 2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, : 60 - 65
- [9] Photonic network-on-chip architecture using 3D integration [J]. OPTOELECTRONIC INTEGRATED CIRCUITS XIII, 2011, 7942
- [10] Deflection Routing in 3D Network-on-Chip with TSV Serialization [J]. 2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 29 - 34