Collaborative Distributed Fault Simulation for Digital Electronic Circuits

被引：0

作者：

Ivask, Eero ^{[1
]}

Devadze, Sergei ^{[1
]}

Ubar, Raimund ^{[1
]}

机构：

[1] Tallinn Univ Technol, EE-12618 Tallinn, Estonia

来源：

INTELLIGENT DISTRIBUTED COMPUTING IV | 2010年 / 315卷

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper we focus on the framework for aggregating adaptively computing resources in different enterprises for computation intensive applications. Concept and implementation of web-based collaborative system was presented to speed up fault simulation and to overcome the problem of memory limits in the case of very large digital circuits. Issues of task partitioning, task allocation, load balancing were handled, credit based priority concept was introduced. Experimental results show feasibility of the solution and gain in performance.

引用

页码：67 / 76

页数：10

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