Very fast chip-level thermal analysis

被引：0

作者：

Nakabayashi, Keiji ^{[1
]}

Nakabayashi, Tamiyo ^{[2
]}

Nakajima, Kazuo ^{[3
]}

机构：

[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara, Japan

[2] Nara Womens Univ, Grad Sch Humanities & Sci, Nara, Turkey

[3] Univ Maryland, Dept Elect & Comp Engn, College Pk, MD 20742 USA

来源：

13TH INTERNATIONAL WORKSHOP ON THERMAL INVESTIGATION OF ICS AND SYSTEMS, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.

引用

页码：82 / +

页数：2

共 50 条

[1] A Survey of Chip-level Thermal Simulators
Sultan, Hameedah
Chauhan, Anjali
Sarangi, Smruti R.
[J]. ACM COMPUTING SURVEYS, 2019, 52 (02)
[2] Accelerated chip-level thermal analysis using multilayer Green's function
Wang, Baohua
Mazumder, Pinaki
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (02) : 325 - 344
[3] Thermal Design, Analysis and Verification of Chip-Level MCM with Properties of Semiconductor Materials
Wu, JunHui
Zhou, Quan
Zhou, Qiang
Chen, Jie
Si, HuiPing
Lin, KaiYan
Zhang, ChiBin
[J]. RESEARCH ON MECHANICS, DYNAMIC SYSTEMS AND MATERIAL ENGINEERING, 2013, 625 : 280 - 286
[4] Analysis and optimization of CDMA systems with chip-level interleavers
Liu, LH
Tong, J
Ping, L
[J]. IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 2006, 24 (01) : 141 - 150
[5] CHIP-LEVEL SIMULATION OF MICROPROCESSORS
ARMSTRONG, JR
WOODRUFF, GW
[J]. COMPUTER, 1980, 13 (01) : 94 - 100
[6] Chip-level microarchitecture trends
Bose, P
[J]. IEEE MICRO, 2004, 24 (02) : 5 - 5
[7] CHIP-LEVEL MODELING WITH HDLS
ARMSTRONG, JR
[J]. IEEE DESIGN & TEST OF COMPUTERS, 1988, 5 (01): : 8 - 18
[8] Dynamic thermal modelling and analysis of press-pack IGBTs both at component-level and chip-level
Busca, Cristian
Teodorescu, Remus
Blaabjerg, Frede
Helle, Lars
Abeyasekera, Tusitha
[J]. 39TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2013), 2013, : 677 - 682
[9] Influence of pulsating submerged liquid jets on chip-level thermal phenomena
Narumanchi, SVJ
Amon, CH
Murthy, JY
[J]. JOURNAL OF ELECTRONIC PACKAGING, 2003, 125 (03) : 354 - 361
[10] Versatile Chip-level Integrated Test Vehicle for Dynamic Thermal Evaluation
Parameswaran, Suresh
Balakrishnan, Saravanan
Ang, Boon
[J]. PROCEEDINGS OF THE 2018 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS), 2018, : 122 - 127

← 1 2 3 4 5 →