Versatile Chip-level Integrated Test Vehicle for Dynamic Thermal Evaluation

被引:0
|
作者
Parameswaran, Suresh [1 ]
Balakrishnan, Saravanan [1 ]
Ang, Boon [1 ]
机构
[1] Xilinx Inc, Silicon Technol Grp, 2100 Log Dr, San Jose, CA 95124 USA
关键词
thermal management; thermal evaluation tool; on-die heating; on-die temperature sensing; package-level thermal evaluation; power-aware testing; thermal-aware testing; on-chip measurements; test-structures;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Thermal management of semiconductor chips is becoming very important as the demand for chip performance increases. It is necessary to evaluate/manage the thermal aspects of a chip throughout the development cycle - starting from initial planning stage to deployment on customer board and beyond. In this paper, we present a versatile thermal evaluation vehicle that addresses the above requirements. This paper describes the circuit architecture/implementation, details of operation, programming aspects, usage model and various applications of a silicon chip that is successfully used as a thermal evaluation tool. The chip has 1600 sectors with programmable heat-generation and temperature-sensing capability - enabling it to generate up to 3W per mm(2) and has a temperature detection range of 30C to 125C with an accuracy of +/-2C. It has a simple implementation and is easy to program and test - yet has substantial thermal evaluation capabilities. It was fabricated in 0.18um technology and packaged as flip-chip. The chip has ability to do automated on-chip temperature measurements through a tester-friendly interface and has been successfully controlled through a simple and inexpensive test-platform. The ability to generate heat on-die and monitor spatial & temporal on-die temperature makes this chip suitable to emulate many different use cases of a product during the development stage ahead of product silicon availability. The capabilities of this test-vehicle make it a suitable candidate for demonstrating poweraware/thermal-aware testing. Silicon measurement data and comparison to simulation results based on numerical models are also presented in this paper.
引用
收藏
页码:122 / 127
页数:6
相关论文
共 50 条
  • [1] A Survey of Chip-level Thermal Simulators
    Sultan, Hameedah
    Chauhan, Anjali
    Sarangi, Smruti R.
    [J]. ACM COMPUTING SURVEYS, 2019, 52 (02)
  • [2] Very fast chip-level thermal analysis
    Nakabayashi, Keiji
    Nakabayashi, Tamiyo
    Nakajima, Kazuo
    [J]. 13TH INTERNATIONAL WORKSHOP ON THERMAL INVESTIGATION OF ICS AND SYSTEMS, PROCEEDINGS, 2007, : 82 - +
  • [3] A chip-level Integrated Optical Spectrometer Based on Pit Interferometers
    Yang, Tao
    Chen, Yuchao
    Li, Xing'ao
    Huang, Wei
    Wang, Qianjin
    Zhu, Yongyuan
    Ho, Hopui
    [J]. 2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2013,
  • [4] Dynamic thermal modelling and analysis of press-pack IGBTs both at component-level and chip-level
    Busca, Cristian
    Teodorescu, Remus
    Blaabjerg, Frede
    Helle, Lars
    Abeyasekera, Tusitha
    [J]. 39TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2013), 2013, : 677 - 682
  • [5] The 5-MINUTE GUIDE to Chip-Level Audio Test
    Knighten, Dan
    [J]. ELECTRONICS WORLD, 2010, 116 (1889): : 18 - 20
  • [6] An unique method to fabricate on-chip capacitors for chip-level EMC evaluation
    Chen, Sheng-Yu
    Siao, Vicky
    [J]. PROCEEDINGS OF THE 2013 20TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2013), 2013, : 366 - 369
  • [7] Synchronizing the IEEE 1149.1 test access port for chip-level testability
    Bhavsar, D
    [J]. IEEE DESIGN & TEST OF COMPUTERS, 2000, 17 (02): : 94 - 99
  • [8] Influence of pulsating submerged liquid jets on chip-level thermal phenomena
    Narumanchi, SVJ
    Amon, CH
    Murthy, JY
    [J]. JOURNAL OF ELECTRONIC PACKAGING, 2003, 125 (03) : 354 - 361
  • [9] Chip-Level and Package-Level Thermal Constraints in Power Semiconductor Switch Modules
    Shenai, Krishna
    [J]. 2015 IEEE INTERNATIONAL WORKSHOP ON INTEGRATED POWER PACKAGING (IWIPP), 2015, : 79 - 82
  • [10] Chip-level charged-device modeling and simulation in CMOS integrated circuits
    Lee, J
    Kim, KW
    Huh, Y
    Bendix, P
    Kang, SM
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2003, 22 (01) : 67 - 81