共 50 条
- [21] Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication [J]. IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2000, 23 (01): : 39 - 47
- [22] Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication [J]. NINETEENTH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM - PROCEEDINGS, 1996 IEMT SYMPOSIUM, 1996, : 130 - 136
- [23] Cycle time reduction at cluster tool in semiconductor wafer fabrication [J]. EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 671 - 677
- [24] Case Study of Cycle Time Reduction by Mechanization in Manufacturing Environment [J]. INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING RESEARCH, 2017, 183
- [26] Microeconomics of yield learning in semiconductor manufacturing [J]. COST AND PERFORMANCE IN INTEGRATED CIRCUIT CREATION, 2003, 5043 : 41 - 56
- [27] THE EFFECTS OF CONTAMINATION ON SEMICONDUCTOR MANUFACTURING YIELD [J]. JOURNAL OF ENVIRONMENTAL SCIENCES, 1988, 31 (02): : 45 - 57
- [28] SHORT CYCLE MANUFACTURING AT MOTOROLA SEMICONDUCTOR [J]. PROCEEDING OF THE TECHNICAL PROGRAM OF NEPCON WEST 89, VOLS 1 AND 2, 1989, : 1331 - 1335
- [29] PRIORITY MIX PLANNING FOR CYCLE TIME-DIFFERENTIATED SEMICONDUCTOR MANUFACTURING SERVICES [J]. 2008 WINTER SIMULATION CONFERENCE, VOLS 1-5, 2008, : 2251 - 2259